The invention concerns a method of adjusting the phase of a clock generator with respect to a data signal. More particularly, it concerns phase and frequency adjustment of a clock generator whose frequency is lower than that of the data signal.
To avoid external synchronization in demultiplexing of a serial data signal it is desirable to regenerate a clock signal on the basis of the incoming data stream. In this connection it is necessary to be able to relate the frequency and phase of the regenerated clock with respect to the data signal. This poses some problems if the bit pattern in the data signal is very irregular.
It is known from e.g. Engel Roza: "Analysis of Phaselocked Timing Extraction Circuits for Pulse Code Transmission", IEEE Transactions on Communications, COM-22, No. 9, p. 1236, September 1974 to regenerate a clock signal by means of analog processing of the incoming data signal. This analog processing consists of a non-linear signal processing with subsequent filtration. The method has the drawback that exact phase reference to data is lost. Further, the dimensioning of such an analog circuit is very complex, so this solution is also vitiated by lack of flexibility.
From EP-A-0 270 236 it is known to control the oscillator of the phase locked loop by detecting the phase difference between the clock signal and the data signal and generating a phase adjustment signal for the clock signal.
Further, in demultiplexing of a data signal, with a view to obtaining an operation frequency as high as possible for the demultiplexer, attention is paid to the implementation of the clock controlled elements since it is usually these which limit the rate. It is therefore preferred that clock controlled elements operate at a lower clock frequency than the data stream. This may be realized with a circuit known per se as shown in FIG. 1, where the first memory elements in the demultiplexer are clocked with a differential clock signal whose frequency is half as great as the frequency of the data signal. The two first memory elements are triggered by the positive clock phase and the negative clock phase, respectively, so that two successive data bits are clocked into their respective memory elements. Since the conversion rate of the demultiplexer is in principle limited by the working rate of the memory elements, this configuration in reality doubles the maximally obtainable rate with respect to the conventional method where the full clock frequency is regenerated. This parallel demultiplexing may moreover be extended to comprise e.g. four input memory elements which are triggered by clock signals with a frequency which is one fourth of the data frequency, the respective clock signals being mutually phase shifted 90.degree..
It is known from EP 0 027 289 to perform phase comparison between a data signal and a clock signal whose frequency is half as great as the frequency of the data signal. However, this known circuit is inexpedient since differentiation and rectification of the data signal are performed prior to the phase comparison, which involves uncertainty in the phase between the regenerated clock and the data signal. Moreover, the circuit comprises delay elements which are to delay the signal corresponding to a phase rotation of 90.degree., which either requires using a clock signal whose frequency is twice as great as the frequency of the data signal, or using a passive delay. The drawbacks of a clock signal having a high frequency are mentioned before, and the use of a passive delay entails that the circuit will be data frequency dependent.
The object of the invention is to provide a digital method in the adjustment of the phase difference of a regenerated clock frequency with respect to a data signal. It is desirable to provide a method entailing that the phase of the clock signal is related directly to the data signal, and where the frequency of the regenerated clock signal is preferably half the frequency of the data signal.